1. Field of the Invention
The present invention relates to semiconductor memories, and in particular, to organization and layout thereof.
2. Description of the Related Art
Semiconductor memories are characterized by regular repetition of memory cells, which are typically organized in an hierarchical addressing topology. Each memory cell is associated with a unique address that typically identifies a particular row and column in a matrix. A group of memory cells is selected by activating a row line (or in some configurations, a word line) to which cells of the group are connected. This enables each of the memory cells so selected, when in a read access mode, to drive its associated column line (or in some configurations, bit-line) in a manner corresponding to the data stored therein. Alternatively, when in a write access mode, each of the selected memory cells is enabled to receive data conveyed on the bit-line to the memory cell.
There are many ways to arrange a bit-line configuration and an associated read circuit. One well-known technique uses a cross-coupled sense amplifier. Typically, a pair of bit-lines couple complementary sides plural of cross-coupled memory cells to a differential amplifier that senses a slight difference in voltage between the two bit-lines and drives a stable, full-level (or full-voltage-swing) signal that may then be further decoded and eventually routed to an output signal path. Sense amplifier circuits are typically constructed from a bi-stable circuit block (such as a cross-coupled differential pair of transistors) that is forced into an unstable state before the bit-lines are to be sensed. During sensing, a slight differential input from the bit-lines pushes the sense amplifier into one of two stable states (e.g., corresponding to a logic "1" or logic "0"). Consequently, conventional sense amplifier circuits can consume significant power while actually sensing the bit-lines.
As memory size increases, fanout and/or downstream signal path impedance tends to increase as bit-lines or sense amplifier output paths span larger proportions of overall layout area. Accordingly, typical speed vs. power trade-offs tend to force larger device sizes, greater power consumption, and/or slower access times. Array partitioning and localized amplification have been used to reduce power consumption in Static Random Access Memories (SRAMs) and thereby improve SRAM speed/power ratios. Two-level sensing has even been used (see e.g., Flannagan et al., 8-ns CMOS 64K.times.4 and 256K.times.1 SRAMs, IEEE Journal of Solid State Circuits, Vol. 25, No. 5, October 1990, pp. 1049-54) with small signal excursions for power reduction.
Nonetheless, memory configurations are desired which even in combination with array subdivision or small-signal techniques may further reduce power consumption or increase access speed. Indeed memory configurations are desired which better optimize area/speed/power tradeoffs. For memory configurations where large numbers of sense amplifiers are defined within submodules or banks and where large numbers of columns are typically read out simultaneously (e.g., in cache memory or embedded memory applications), area/speed/power tradeoffs associated with submodule- or bank-resident sense amplifiers, or more generally with read data paths, are important. Improved memory configurations are desired.